S93WD662/S93WD663
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operationisnotcompleted, whileDOhighindicatesthat
the device is ready for the next instruction. See the
Applications Aid section for detailed use of the ready
busy status.
databitswilltoggleontherisingedgeoftheSKclockand
are stable after the specified time delay
(tPD0 or tPD1).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (tCSMIN). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93WD662/WD663 can be determined by
selecting the device and polling the DO pin.
The format for all instructions is: one start bit; two op
code bits and either eight (x16) or nine (x8) address or
instruction bits.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93WD662/
WD663 will come out of the high impedance state and,
will first output an initial dummy zero bit, then begin
shifting out the data addressed (MSB first). The output
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of 250ns (tCSMIN). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93WD662/WD663 can be
t
t
t
SKLOW
CSH
SKHI
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATAVALID
2013 ILL 3 1.0
Figure 1. Sychronous Data Timing
SK
t
CS
CS
DI
STANDBY
A
N
A
N–1
A
0
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
N
D
N–1
D
1
D
0
2013 ILL4 1.0
Figure 2. Read Instruction Timing
2013 2.1 8/2/00
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
