5 Operation Description
VIPer50A-E/ASP-E
Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down
D2
D3
VIPer50
VIPer50
VDD
DRAIN
R1
-
VDD
DRAIN
OSC
R3
R2
Q2
-
13V
+
OSC
COMP SOURCE
13V
+
D1
AUXILIARY
WINDING
COMP SOURCE
R3
R2
Q1
C4
R1
R4
C3
C2
+
+
C1
Shutdown
D1
FC00331
FC00340
Figure 19. Typical Compensation Network
Figure 20. Slope Compensation
VIPer50
VDD
DRAIN
-
R2
R1
OSC
VIPer50
13V
+
VDD
13V
DRAIN
COMP SOURCE
-
OSC
+
COMP SOURCE
R1
C1
C2
C2
Q1
R3
C3
C1
FC00351
FC00361
Figure 21. External Clock Synchronization
Figure 22. Current Limitation Circuit Example
VIPer50
VDD
DRAIN
-
VIPer50
OSC
13V
+
VDD
DRAIN
COMP SOURCE
-
OSC
13V
+
COMP SOURCE
10 k
Ω
R1
Q1
R2
FC00370
FC00380
20/31
STMICROELECTRONICS [ ST ]
