VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ORDERING NUMBERS
PENTAWATT HV
VIPer20
PENTAWATT HV (022Y)
PowerSO-10™
VIPer20SP
DIP-8
VIPer20 (022Y)
VIPer20A (022Y)
VIPer20DIP
VIPer20ADIP
VIPer20A
VIPer20ASP
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
source, and can easily be connected to the
output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the VDD
voltage, which cannot overpass 13V. The
output voltage will be somewhat higher than the
nominal one, but still under control.
COMP PIN:
This pin provides two functions:
SOURCE Pin:
Power MOSFET source pin. Primary side circuit
common ground connection.
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can easily be adjusted to the
needed value with usual components value. As
VDD Pin:
This pin provides two functions:
stated
above,
secondary
regulation
- It corresponds to the low voltage supply of the
control part of the circuit. If VDD goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the VDD pin sources a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
configurations are also implemented through
the COMP pin.
- When the COMP voltage goes below 0.5V, the
shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain VDD at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put on VDD pin by transformer
design, in order to stick the output of the
transconductance amplifier to the high state.
The COMP pin behaves as a constant current
OSC PIN:
An Rt-Ct network must be connected on that pin to
define the switching frequency. Note that despite
the connection of Rt to VDD, no significant
frequency change occurs for VDD varying from 8V
to 15V. It also provides a synchronization
capability, when connected to an external
frequency source.
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STMICROELECTRONICS [ ST ]
