USBLC6-2
Technical information
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see
Figure 6.
ESD behavior: parasitic phenomena due to unsuitable layout
ESD surge on data line
V
BUS
Data line
L
I/O
L
I/O
di
dt
L
VBUS
V
CC
pin
V
F
V
TRANSIL
I/O pin
V
CL
V
TRANSIL
+ V
F
t
t
r
= 1 ns
GND pin
t
r
= 1 ns
L
GND
L
GND
di
dt
- V
F
t
L
I/O
di + L
GND
di
dt
dt
V
CL+
Positive
Surge
V
CL
+ = V
TRANSIL
+ V
F
+ L
I/O
di + L
GND
di
dt
dt
V
CL-
= -V
F
- L
I/O
di - L
GND
di
dt
dt
V TRANSIL
=
VBR
+
Rd.Ip
surge > 0
surge > 0
-L
I/O
di - L
GND
di
dt
dt
Negative
Surge
V
CL-
2.3
How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to V
BUS
pin and from GND plane to GND pin must be as short as
possible to avoid overvoltages due to parasitic phenomena (see
and
for
layout consideration)
Figure 7.
ESD behavior: layout optimization
Figure 8.
ESD behavior: measurement
conditions
1
1
6
ESD SURGE
2
5
3
4
TEST BOARD
IN
OUT
USBLC6-2SC6
Unsuitable layout
1
1
6
+5 V
2
5
3
4
Optimized layout
5/14
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