TDA7309
SDA, SCL I2CBUS TIMING
Symbol
Parameter
Min.
0
Typ.
Max.
Unit
kHz
µs
fSCL
tBUF
SCL clock frequency
400
Bus free time between a STOP and START condition
1.3
0.6
tHD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
s
µ
tLOW
tHIGH
tSU:STA
tHD:DA
tSU:DAT
tR
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
1.3
0.6
µs
µs
0.6
µs
0.300
100
20
µs
Data set-up time
ns
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
300
300
ns (*)
ns (*)
µs
tF
20
tSU:STO
0.6
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I2C BUS master.
Definition of timing on the I2C-bus
SDA
t
BUF
t
R
t
F
t
t
SU;STO
HIGH
t
t
SP
HD;STA
SCL
t
t
SU;STA
LOW
t
F
t
HD;DAT
t
t
SU;DAT
HD;STA
P
S
Sr
P
D95AU314
P = STOP
S = START
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STMICROELECTRONICS [ ST ]
