STM8S207xx, STM8S208xx
Table 13. Option byte description (continued)
Option bytes
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
OPT4
PRSC[1:0] AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilisation time.
0x00: 2048 HSE cycles
OPT5
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6
OPT7
Reserved
WAITSTATE Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
1 wait state is required if fCPU > 16 MHz.
0: No wait state
1: 1 wait state
Doc ID 14733 Rev 9
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STMICROELECTRONICS [ ST ]
