Interrupt vector mapping
STM8S207xx, STM8S208xx
7
Interrupt vector mapping
Table 11. Interrupt mapping
IRQ
no.
Source
block
Wakeup from
halt mode
Wakeup from
active-halt mode
Description
Vector address
RESET
TRAP
TLI
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
Software interrupt
0
1
External top level interrupt
Auto wake up from halt
Clock controller
-
-
AWU
-
Yes
-
2
CLK
-
3
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
beCAN
beCAN
SPI
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
beCAN RX interrupt
Yes(1)
Yes
Yes
Yes
Yes
Yes
-
Yes(1)
Yes
Yes
Yes
Yes
Yes
-
4
5
6
7
8
9
beCAN TX/ER/SC interrupt
End of transfer
10
Yes
Yes
TIM1 update/overflow/underflow/
trigger/break
11
TIM1
-
-
0x00 8034
12
13
14
15
16
17
18
19
20
21
22
23
24
TIM1
TIM2
TIM1 capture/compare
TIM2 update /overflow
TIM2 capture/compare
Update/overflow
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
0x00 8068
-
-
TIM2
-
-
TIM3
-
-
TIM3
Capture/compare
-
-
UART1
UART1
I2C
Tx complete
-
-
Receive register DATA FULL
I2C interrupt
-
-
Yes
Yes
UART3
UART3
ADC2
TIM4
Tx complete
-
-
-
-
-
-
-
-
-
-
Receive register DATA FULL
ADC2 end of conversion
TIM4 update/overflow
EOP/WR_PG_DIS
Flash
0x00 806C to
0x00 807C
Reserved
1. Except PA1
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Doc ID 14733 Rev 9
STMICROELECTRONICS [ ST ]
