STM8S207xx, STM8S208xx
Electrical characteristics
10.3.10 10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
, and T unless otherwise
DDA MASTER
A
Table 44. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
4
Unit
V
DDA = 3 to 5.5 V
1
fADC
ADC clock frequency
MHz
VDDA = 4.5 to 5.5 V
1
3
6
VDDA Analog supply
5.5
VDDA
V
V
VREF+ Positive reference voltage
VREF- Negative reference voltage
2.75(1)
VSSA
VSSA
0.5(1)
VDDA
V
V
VAIN
Conversion voltage range(2)
Devices with external
REF+/VREF- pins
VREF-
VREF+
V
V
Internal sample and hold
capacitor
CADC
3
pF
f
ADC = 4 MHz
0.75
0.5
7
(2)
tS
Sampling time
µs
fADC = 6 MHz
tSTAB Wakeup time from standby
µs
µs
fADC = 4 MHz
3.5
2.33
14
Total conversion time (including
tCONV
fADC = 6 MHz
µs
sampling time, 10-bit resolution)
1/fADC
1. Data guaranteed by design, not tested in production..
2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
Doc ID 14733 Rev 9
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STMICROELECTRONICS [ ST ]
