STM8S207xx, STM8S208xx
Pinouts and pin description
Table 6.
Pin description (continued)
Pin number
Input
Output
Alternate
Default
function
Pin name
alternate
after remap
function
[option bit]
65 51
66 52
-
-
-
-
-
-
PG7
PE4
I/O
I/O
X
X
X
X
O1
O1
X
X
X
X
Port G7
X
X
Port E4
Port E3
Timer 1 -
break input
67 53 37
-
-
PE3/TIM1_BKIN I/O
X
X
O1
X
X
68 54 38 34
69 55 39 35
-
-
PE2/I2C_SDA
PE1/I2C_SCL
I/O
I/O
X
X
X
X
O1 T(3)
O1 T(3)
Port E2 I2C data
Port E1 I2C clock
Configurable
clock output
70 56 40 36
-
PE0/CLK_CCO
I/O
X
X
X
HS O3
X
X
Port E0
71
72
-
-
-
-
-
-
-
-
PI6
PI7
I/O
I/O
X
X
X
X
O1
O1
X
X
X
X
Port I6
Port I7
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
Timer 3 -
channel 2
73 57 41 37 25 PD0/TIM3_CH2
I/O
X
X
X
HS O3
X
X
Port D0
SWIM data
interface
74 58 42 38 26 PD1/SWIM
75 59 43 39 27 PD2/TIM3_CH1
76 60 44 40 28 PD3/TIM2_CH2
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS O4
HS O3
HS O3
HS O3
O1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
Timer 2 -
channel 2
ADC_ETR
[AFR0]
PD4/TIM2_CH1/B
Timer 2 -
channel 1
BEEP output
[AFR7]
77 61 45 41 29
EEP
UART3 data
transmit
78 62 46 42 30 PD5/ UART3_TX I/O
PD6/
UART3 data
receive
79 63 47 43 31
I/O
I/O
O1
UART3_RX(1)
Top level
interrupt
TIM1_CH4
[AFR4]
80 64 48 44 32 PD7/TLI
O1
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as
part of the bootloader activation process and returned to the floating state before a return from the bootloader.
2. The beCAN interface is available on STM8S208xx devices only
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented).
Doc ID 14733 Rev 9
31/103
STMICROELECTRONICS [ ST ]
