STM8S003F3 STM8S003K3
Block diagram
3
Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
Reset block
Reset
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock controller
Detector
Reset
POR
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interface
Debug/SWIM
8 Kbyte
program Flash
128 byte
data EEPROM
400 Kbit/s
8 Mbit/s
I2C
1 Kbyte RAM
Up to
4 CAPCOM
channels
SPI
16-bit advanced control
timer (TIM1)
+ 3 complementary
outputs
LIN master
SPI emul.
UART2
Up to
3 CAPCOM
channels
16-bit general purpose
timer (TIM2)
up to 5
channels
ADC1
8-bit basic timer
(TIM4)
1/2/4 kHz beep
Beeper
AWU timer
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