Electrical characteristics
STM8S003K3 STM8S003F3
Figure 9: fCPUmax versus VDD
f
(MHz)
CPU
Functionality
not
16
12
8
guaranteed
in this area
Functionality guaranteed
@T -40 to 85 °C
A
4
0
4.0
Supply voltage
2.95
5.0
5.5
Table 19: Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
2
∞
tVDD
μs/V
VDD fall time rate(1)
2
∞
tTEMP
VIT+
VIT-
Reset release delay
VDD rising
1.7
2.85
2.8
ms
V
Power-on reset threshold
Brown-out reset threshold
2.6
2.5
2.7
2.65
70
VHYS(BOR) Brown-out reset hysteresis
mV
(1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
Figure 10: External capacitor CEXT
C
ESR
ESL
Rleak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
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STMICROELECTRONICS [ ST ]
