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STM8S003F3P6 参数 Datasheet PDF下载

STM8S003F3P6图片预览
型号: STM8S003F3P6
PDF下载: 下载PDF文件 查看货源
内容描述: 价值线, 16兆赫STM8S 8位MCU , 8 KB闪存, 128字节的数据EEPROM , 10位ADC , 3个定时器, UART , SPI , I& SUP2 ; ç [Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 99 页 / 952 K
品牌: STMICROELECTRONICS [ ST ]
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Product overview  
STM8S003K3 STM8S003F3  
The UBC area remains write-protected during in-application programming. This means that  
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot  
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the  
IAP and communication routines.  
Figure 2: Flash memory organization  
Option bytes  
Data EEPROM (128 bytes)  
Programmable  
area from 64  
UBC area  
bytes(1 page)  
Remains write protected during IAP  
up to 8 Kbytes  
(in 1 page steps)  
Low density  
Flash program  
memory  
(8 Kbytes)  
Program memory area  
Write access possible for IAP  
Read-out protection (ROP)  
The read-out protection blocks reading and writing from/to the Flash program memory and  
the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated,  
any attempt to toggle its status triggers a global erase of the program memory. Even if no  
protection can be considered as totally unbreakable, the feature provides a very high level  
of protection for a general purpose microcontroller.  
4.5  
Clock controller  
The clock controller distributes the system clock (fMASTER) coming from different oscillators  
to the core and the peripherals. It also manages clock gating for low power modes and ensures  
clock robustness.  
Features  
Clock prescaler: To get the best compromise between speed and current consumption  
the clock frequency to the CPU and peripherals can be adjusted by a programmable  
prescaler.  
Safe clock switching: Clock sources can be changed safely on the fly in run mode  
through a configuration register. The clock signal is not switched until the new clock source  
is ready. The design guarantees glitch-free switching.  
Clock management: To reduce power consumption, the clock controller can stop the  
clock to the core, individual peripherals or memory.  
Master clock sources: Four different clock sources can be used to drive the master  
clock:  
1-16 MHz high-speed external crystal (HSE)  
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)  
-
16 MHz high-speed internal RC oscillator (HSI)  
-
128 kHz low-speed internal RC (LSI)  
-
12/99  
DocID018576 Rev 2  
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