STM32F103xC, STM32F103xD, STM32F103xE
Table 5.
LFBGA144
LFBGA100
Pinouts and pin descriptions
High-density STM32F103xx pin definitions (continued)
I / O Level
(2)
Pins
WLCSP64
LQFP100
LQFP144
LQFP64
Pin name
Type
(1)
Alternate functions
(4)
Main
function
(3)
(after reset)
Default
Remap
A7
A7 A4 55 89 133
PB3/
I/O FT
JTDO
SPI3_SCK / I2S3_CK/
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
PB4 / TIM3_CH1
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
USART1_TX
USART1_RX
A6
A6 B4 56 90 134
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
V
SS_3
V
DD_3
I/O FT
I/O
I/O FT
I/O FT
I
I/O FT
I/O FT
I/O FT
I/O FT
S
S
NJTRST
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
V
SS_3
V
DD_3
SPI3_MISO
I2C1_SMBA/ SPI3_MOSI
I2S3_SD
I2C1_SCL
(8)
/ TIM4_CH1
(8)
I2C1_SDA
(8)
/
FSMC_NADV /
TIM4_CH2
(8)
B6 C5 A5 57 91 135
C6 B5 B5 58 92 136
D6 A5 C5 59 93 137
D5 D5 A6 60 94 138
C5 B4 D5 61 95 139
B5
A4 B6 62 96 140
-
-
-
-
97 141
98 142
TIM4_CH3
(8)
/SDIO_D4
TIM4_CH4
(8)
/SDIO_D5
TIM4_ETR / FSMC_NBL0
FSMC_NBL1
I2C1_SCL/
CAN_RX
I2C1_SDA /
CAN_TX
A5 D4
A4 C4
E5
F5
E5 A7 63 99 143
F5 A8 64 100 144
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V
REF+
functionality is provided instead.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and
LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,
refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
10. For devices delivered in LQFP64 packages, the FSMC function is not available.
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