STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.19
Table 62.
Symbol
V
DDA
V
REF+
V
SSA
R
LOAD(1)
R
O(1)
DAC electrical specifications
DAC characteristics
Parameter
Analog supply voltage
Reference supply voltage
Ground
Min
2.4
2.4
0
Typ
3.6
3.6
0
Max
Unit
V
V
V
k
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
and V
SS
to have a 1% accuracy is
1.5 M
Maximum capacitive load at
DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at V
REF+
= 3.6 V
and (0x155) and (0xEAB) at V
REF+
=
2.4 V
V
REF+
must always be below V
DDA
Comments
Resistive load with buffer ON 5
Impedance output with buffer
OFF
15
k
C
LOAD(1)
Capacitive load
50
pF
DAC_OUT Lower DAC_OUT voltage
min
(1)
with buffer ON
DAC_OUT Higher DAC_OUT voltage
with buffer ON
max
(1)
DAC_OUT Lower DAC_OUT voltage
min
(1)
with buffer OFF
DAC_OUT Higher DAC_OUT voltage
with buffer OFF
max
(1)
I
DDVREF+
DAC DC current
consumption in quiescent
mode (Standby mode)
0.2
V
V
DDA
– 0.2
0.5
V
mV
It gives the maximum output
excursion of the DAC.
V
REF+
– 1LSB V
With no load, worst code (0xF1C) at
V
REF+
= 3.6 V in terms of DC
consumption on the inputs
With no load, middle code (0x800) on
the inputs
With no load, worst code (0xF1C) at
V
REF+
= 3.6 V in terms of DC
consumption on the inputs
Given for the DAC in 10-bit
configuration
Given for the DAC in 12-bit
configuration
Given for the DAC in 10-bit
configuration
Given for the DAC in 12-bit
configuration
220
µA
380
I
DDA
DAC DC current
consumption in quiescent
mode (Standby mode)
µA
480
µA
DNL
(2)
Differential non linearity
Difference between two
consecutive code-1LSB)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
±0.5
LSB
±2
±1
LSB
LSB
INL
(2)
±4
LSB
Doc ID 14611 Rev 7
103/123
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