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STM32F103R4T7TR 参数 Datasheet PDF下载

STM32F103R4T7TR图片预览
型号: STM32F103R4T7TR
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ARM的低密度高性能线的32位MCU,具有16或32 KB闪存, USB , CAN ,6个定时器, 2的ADC ,6个通信接口 [Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces]
分类和应用: 闪存微控制器和处理器外围集成电路通信时钟
文件页数/大小: 80 页 / 1067 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F103x4, STM32F103x6  
Figure 2. Clock tree  
Description  
8 MHz  
HSI RC  
HSI  
USBCLK  
to USB interface  
USB  
Prescaler  
/1, 1.5  
48 MHz  
/2  
HCLK  
72 MHz max  
Clock  
to AHB bus, core,  
memory and DMA  
Enable (3 bits)  
to Cortex System timer  
/8  
SW  
PLLSRC  
FCLK Cortex  
free running clock  
36 MHz max  
PLLMUL  
HSI  
AHB  
Prescaler  
/1, 2..512  
APB1  
Prescaler  
/1, 2, 4, 8, 16  
SYSCLK  
..., x16  
x2, x3, x4  
PLL  
PCLK1  
PLLCLK  
HSE  
72 MHz  
max  
to APB1  
peripherals  
Peripheral Clock  
Enable (13 bits)  
TIM2, TIM3  
If (APB1 prescaler =1) x1  
else x2  
to TIM2, TIM3  
TIMXCLK  
Peripheral Clock  
Enable (3 bits)  
CSS  
APB2  
Prescaler  
/1, 2, 4, 8, 16  
PLLXTPRE  
/2  
72 MHz max  
PCLK2  
to APB2  
OSC_OUT  
peripherals  
4-16 MHz  
HSE OSC  
Peripheral Clock  
Enable (11 bits)  
OSC_IN  
TIM1 timer  
If (APB2 prescaler =1) x1  
else x2  
to TIM1  
TIM1CLK  
Peripheral Clock  
Enable (1 bit)  
to ADC  
/128  
LSE  
ADC  
Prescaler  
/2, 4, 6, 8  
OSC32_IN  
to RTC  
LSE OSC  
ADCCLK  
RTCCLK  
32.768 kHz  
OSC32_OUT  
RTCSEL[1:0]  
to Independent Watchdog (IWDG)  
IWDGCLK  
LSI  
LSI RC  
40 kHz  
Legend:  
HSE = high-speed external clock signal  
HSI = high-speed internal clock signal  
LSI = low-speed internal clock signal  
LSE = low-speed external clock signal  
Main  
Clock Output  
/2  
PLLCLK  
MCO  
HSI  
HSE  
SYSCLK  
MCO  
ai15176  
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is  
64 MHz.  
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either  
48 MHz or 72 MHz.  
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.  
Doc ID 15060 Rev 3  
11/80  
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