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STM32F103R4T7TR 参数 Datasheet PDF下载

STM32F103R4T7TR图片预览
型号: STM32F103R4T7TR
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ARM的低密度高性能线的32位MCU,具有16或32 KB闪存, USB , CAN ,6个定时器, 2的ADC ,6个通信接口 [Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces]
分类和应用: 闪存微控制器和处理器外围集成电路通信时钟
文件页数/大小: 80 页 / 1067 K
品牌: STMICROELECTRONICS [ ST ]
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Description  
STM32F103x4, STM32F103x6  
This hardware block provides flexible interrupt management features with minimal interrupt  
latency.  
2.3.6  
External interrupt/event controller (EXTI)  
The external interrupt/event controller consists of 19 edge detector lines used to generate  
interrupt/event requests. Each line can be independently configured to select the trigger  
event (rising edge, falling edge, both) and can be masked independently. A pending register  
maintains the status of the interrupt requests. The EXTI can detect an external line with a  
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected  
to the 16 external interrupt lines.  
2.3.7  
Clocks and startup  
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is  
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in  
which case it is monitored for failure. If failure is detected, the system automatically switches  
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full  
interrupt management of the PLL clock entry is available when necessary (for example on  
failure of an indirectly used external crystal, resonator or oscillator).  
Several prescalers allow the configuration of the AHB frequency, the high-speed APB  
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and  
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed  
APB domain is 36 MHz. See Figure 2 for details on the clock tree.  
2.3.8  
2.3.9  
Boot modes  
At startup, boot pins are used to select one of three boot options:  
Boot from User Flash  
Boot from System Memory  
Boot from embedded SRAM  
The boot loader is located in System Memory. It is used to reprogram the Flash memory by  
using USART1. For further details please refer to AN2606.  
Power supply schemes  
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.  
DD  
Provided externally through V pins.  
DD  
V
, V  
= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs  
DDA  
SSA  
and PLL (minimum voltage to be applied to V  
is 2.4 V when the ADC is used).  
DDA  
V
and V  
must be connected to V and V , respectively.  
DDA  
SSA DD SS  
V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup  
BAT  
registers (through power switch) when V is not present.  
DD  
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.  
2.3.10  
Power supply supervisor  
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is  
always active, and ensures proper operation starting from/down to 2 V. The device remains  
14/80  
Doc ID 15060 Rev 3  
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