STM32F103x4, STM32F103x6
Table 56. Document revision history (continued)
Revision history
Date
Revision
Changes
Note 5 updated and Note 4 added in Table 5: Low-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 12: Embedded internal reference
voltage. Typical IDD_VBAT value added in Table 16: Typical and
maximum current consumptions in Stop and Standby modes.
Figure 14: Typical current consumption on VBAT with RTC on versus
temperature at different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables. Table 24: HSI
oscillator characteristics modified. Conditions removed from Table 26:
Low-power mode wakeup timings.
24-Sep-2009
3
Note 1 modified below Figure 20: Typical application with an 8 MHz
crystal.
Figure 23: Recommended NRST pin protection modified.
Jitter added to Table 27: PLL characteristics on page 48.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 49.
CADC and RAIN parameters modified in Table 45: ADC characteristics.
RAIN max values modified in Table 46: RAIN max for fADC = 14 MHz.
Small text changes.
Doc ID 15060 Rev 3
79/80
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