Electrical characteristics
Static latch-up
STM32F103xC, STM32F103xD, STM32F103xE
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
●
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA +105 °C conforming to JESD78A
II level A
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 45. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
–0.5
0.8
V
Standard IO input high level voltage
IO FT(1) input high level voltage
Input low level voltage
TTL ports
2
2
VDD+0.5
5.5V
VIH
VIL
VIH
–0.5
0.35 VDD
VDD+0.5
CMOS ports
V
Input high level voltage
0.65 VDD
Standard IO Schmitt trigger voltage
hysteresis(2)
200
mV
mV
Vhys
IO FT Schmitt trigger voltage
hysteresis(2)
(3)
5% VDD
VSS VIN VDD
Standard I/Os
1
Ilkg
Input leakage current (4)
µA
VIN= 5 V, I/O FT
VIN VSS
3
RPU
RPD
CIO
Weak pull-up equivalent resistor(5)
Weak pull-down equivalent resistor(5)
I/O pin capacitance
30
30
40
40
5
50
50
k
k
pF
VIN VDD
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ ST ]
