Revision history
Table 72. Document revision history
STM32F103xC, STM32F103xD, STM32F103xE
Changes
Date
Revision
Figure 1: STM32F103xC, STM32F103xD and STM32F103xE
performance line block diagram updated.
Note 5 updated and Note 4 added in Table 5: High-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 13: Embedded internal reference
voltage.
Table 16: Maximum current consumption in Sleep mode, code running
from Flash or RAM modified.
fHSE_ext min modified in Table 21: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator
characteristics and Table 24: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables.
Note 1 modified below Figure 22: Typical application with an 8 MHz
crystal. Table 25: HSI oscillator characteristics modified. Conditions
removed from Table 27: Low-power mode wakeup timings.
Jitter added to Table 28: PLL characteristics.
Figure 43: Recommended NRST pin protection modified.
In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
timings: th(BL_NOE) and th(A_NOE) modified.
21-Jul-2009
6
In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings: th(A_NWE) and th(Data_NWE) modified.
In Table 33: Asynchronous multiplexed PSRAM/NOR read timings:
th(AD_NADV) and th(A_NOE) modified.
In Table 34: Asynchronous multiplexed PSRAM/NOR write timings:
th(A_NWE) modified.
In Table 35: Synchronous multiplexed NOR/PSRAM read timings:
th(CLKH-NWAITV) modified.
In Table 40: Switching characteristics for NAND Flash read and write
cycles: th(NOE-D) modified.
Table 52: SPI characteristics modified. Values added to Table 53: I2S
characteristics and Table 54: SD / MMC characteristics.
CADC and RAIN parameters modified in Table 58: ADC characteristics.
RAIN max values modified in Table 59: RAIN max for fADC = 14 MHz.
Table 62: DAC characteristics modified. Figure 57: 12-bit buffered /non-
buffered DAC added.
Figure 60: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline and Table 65: LFBGA100 - 10 x 10 mm low profile fine
pitch ball grid array package mechanical data updated.
Number of DACs corrected in Table 3: STM32F103xx family.
IDD_VBAT updated in Table 17: Typical and maximum current
consumptions in Stop and Standby modes.
Figure 16: Typical current consumption on VBAT with RTC on vs.
temperature at different VBAT values added.
24-Sep-2009
7
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.11: EMC characteristics on page 80.
Table 62: DAC characteristics modified. Small text changes.
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ ST ]
