STM32F103xC, STM32F103xD, STM32F103xE
Description
Figure 2.
Clock tree
USBCLK
to USB interface
USB
Prescaler
/1, 1.5
48 MHz
I2S3CLK
to I2S3
Peripheral clock
enable
I2S2CLK
to I2S2
Peripheral clock
enable
SDIOCLK
to SDIO
8 MHz
Peripheral clock
HSI
HSI RC
enable
FSMCCLK
to FSMC
Peripheral clock
enable
/2
HCLK
to AHB bus, core,
memory and DMA
72 MHz max
Clock
Enable (4 bits)
/8
to Cortex System timer
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
APB1
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
Prescaler
Prescaler
PLLCLK
HSE
72 MHz
max
to APB1
/1, 2..512
/1, 2, 4, 8, 16
peripherals
Peripheral Clock
Enable (20 bits)
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
else x2
to TIM2,3,4,5,6 and 7
TIMXCLK
CSS
Peripheral Clock
Enable (6 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
72 MHz max
PCLK2
OSC_OUT
OSC_IN
peripherals to APB2
4-16 MHz
HSE OSC
Peripheral Clock
Enable (15 bits)
TIM1 & 8 timers
If (APB2 prescaler =1) x1
else x2
to TIM1 and TIM8
TIMxCLK
Peripheral Clock
Enable (2 bit)
to ADC1, 2 or 3
/128
LSE
ADC
Prescaler
/2, 4, 6, 8
OSC32_IN
to RTC
LSE OSC
ADCCLK
RTCCLK
32.768 kHz
OSC32_OUT
HCLK/2
/2
RTCSEL[1:0]
To SDIO AHB interface
Peripheral clock
enable
to Independent Watchdog (IWDG)
IWDGCLK
LSI
LSI RC
40 kHz
Legend:
Main
Clock Output
/2
PLLCLK
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
MCO
HSI
HSE
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
SYSCLK
MCO
ai14752b
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
48 MHz or 72 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
Doc ID 14611 Rev 7
13/123
STMICROELECTRONICS [ ST ]
