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STM32F103R4H6XXX 参数 Datasheet PDF下载

STM32F103R4H6XXX图片预览
型号: STM32F103R4H6XXX
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ARM的低密度高性能线的32位MCU,具有16或32 KB闪存, USB , CAN ,6个定时器, 2的ADC ,6个通信接口 [Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces]
分类和应用: 闪存通信
文件页数/大小: 80 页 / 1067 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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STM32F103x4, STM32F103x6
Electrical characteristics
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 32.
Symbol
V
ESD(HBM)
ESD absolute maximum ratings
Ratings
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device
model)
Conditions
T
A
�½+25
°C
conforming to
JESD22-A114
T
A
�½+25
°C
conforming to
JESD22-C101
Class
2
Maximum value
(1)
2000
V
II
500
Unit
V
ESD(CDM)
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 33.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
Conditions
T
A
�½+105
°C conforming to JESD78A
Class
II level A
Doc ID 15060 Rev 3
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