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STM32F100C8T6BTR 参数 Datasheet PDF下载

STM32F100C8T6BTR图片预览
型号: STM32F100C8T6BTR
PDF下载: 下载PDF文件 查看货源
内容描述: 低和中等密度值线,先进的基于ARM的32位MCU低和中等密度值线,先进的基于ARM的32位MCU [Low & medium-density value line, advanced ARM-based 32-bit MCU Low & medium-density value line, advanced ARM-based 32-bit MCU]
分类和应用:
文件页数/大小: 84 页 / 1148 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB  
Description  
2.6  
Nested vectored interrupt controller (NVIC)  
The STM32F100xx value line embeds a nested vectored interrupt controller able to handle  
up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)  
and 16 priority levels.  
Closely coupled NVIC gives low latency interrupt processing  
Interrupt entry vector table address passed directly to the core  
Closely coupled NVIC core interface  
Allows early processing of interrupts  
Processing of late arriving higher priority interrupts  
Support for tail-chaining  
Processor state automatically saved  
Interrupt entry restored on interrupt exit with no instruction overhead  
This hardware block provides flexible interrupt management features with minimal interrupt  
latency.  
2.7  
2.8  
External interrupt/event controller (EXTI)  
The external interrupt/event controller consists of 18 edge detector lines used to generate  
interrupt/event requests. Each line can be independently configured to select the trigger  
event (rising edge, falling edge, both) and can be masked independently. A pending register  
maintains the status of the interrupt requests. The EXTI can detect an external line with a  
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected  
to the 16 external interrupt lines.  
Clocks and startup  
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is  
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in  
which case it is monitored for failure. If failure is detected, the system automatically switches  
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full  
interrupt management of the PLL clock entry is available when necessary (for example on  
failure of an indirectly used external crystal, resonator or oscillator).  
Several prescalers allow the configuration of the AHB frequency, the high-speed APB  
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and  
the APB domains is 24 MHz.  
2.9  
Boot modes  
At startup, boot pins are used to select one of three boot options:  
Boot from user Flash  
Boot from system memory  
Boot from embedded SRAM  
The boot loader is located in System Memory. It is used to reprogram the Flash memory by  
using USART1. For further details please refer to AN2606.  
Doc ID 16455 Rev 2  
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