Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 42. I/O AC characteristics definition
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 45).
PU
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10.
Table 48. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.5
2
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
200
40
mV
Weak pull-up equivalent resistor(2)
VIN VSS
30
50
k
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
100
(1)
VNF(NRST)
NRST Input not filtered pulse
300
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 43. Recommended NRST pin protection
V
DD
External
reset circuit(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 µF
STM32F10xxx
ai14132c
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset will not be taken into account by the device.
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ ST ]
