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STM32F103RDY6XXXTR 参数 Datasheet PDF下载

STM32F103RDY6XXXTR图片预览
型号: STM32F103RDY6XXXTR
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 闪存微控制器和处理器外围集成电路装置通信时钟
文件页数/大小: 123 页 / 1691 K
品牌: STMICROELECTRONICS [ ST ]
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Electrical characteristics  
STM32F103xC, STM32F103xD, STM32F103xE  
5.3.8  
PLL characteristics  
The parameters given in Table 28 are derived from tests performed under ambient  
temperature and V supply voltage conditions summarized in Table 10.  
DD  
Table 28. PLL characteristics  
Value  
Symbol  
Parameter  
Unit  
Min  
Typ  
Max(1)  
PLL input clock(2)  
1
8.0  
25  
60  
MHz  
%
fPLL_IN  
PLL input clock duty cycle  
PLL multiplier output clock  
PLL lock time  
40  
16  
fPLL_OUT  
tLOCK  
72  
MHz  
µs  
200  
300  
Jitter  
Cycle-to-cycle jitter  
ps  
1. Based on characterization, not tested in production.  
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with  
the range defined by fPLL_OUT  
.
5.3.9  
Memory characteristics  
Flash memory  
The characteristics are given at T = –40 to 105 °C unless otherwise specified.  
A
Table 29. Flash memory characteristics  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max(1) Unit  
tprog  
16-bit programming time TA–40 to +105 °C  
40  
20  
20  
52.5  
70  
40  
40  
µs  
ms  
ms  
tERASE Page (2 KB) erase time TA –40 to +105 °C  
tME  
Mass erase time  
Supply current  
TA –40 to +105 °C  
Read mode  
fHCLK = 72 MHz with 2 wait  
states, VDD = 3.3 V  
28  
mA  
Write mode  
fHCLK = 72 MHz, VDD = 3.3 V  
7
5
mA  
mA  
IDD  
Erase mode  
fHCLK = 72 MHz, VDD = 3.3 V  
Power-down mode / Halt,  
50  
µA  
V
VDD = 3.0 to 3.6 V  
Vprog Programming voltage  
2
3.6  
1. Guaranteed by design, not tested in production.  
60/123  
Doc ID 14611 Rev 7