STM32F103x8, STM32F103xB
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in
are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
All I/Os are CMOS and TTL compliant.
Table 35.
Symbol
V
OL(1)
V
OH(2)
V
OL (1)
V
OH (2)
V
OL(1)(3)
V
OH(2)(3)
V
OL(1)(3)
V
OH(2)(3)
Output voltage characteristics
Parameter
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Conditions
TTL port
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
CMOS port
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
Min
Max
0.4
V
V
DD
–0.4
0.4
V
2.4
1.3
V
V
DD
–1.3
0.4
V
V
DD
–0.4
Unit
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
2. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
3. Based on characterization data, not tested in production.
Doc ID 13587 Rev 12
61/96
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