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STM32F103C8T7 参数 Datasheet PDF下载

STM32F103C8T7图片预览
型号: STM32F103C8T7
PDF下载: 下载PDF文件 查看货源
内容描述: 中密度高性能线的基于ARM的32位MCU,具有64或128 KB的闪存, USB , CAN ,7个定时器, 2的ADC , 9融为一体。接口 [Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces]
分类和应用: 闪存
文件页数/大小: 105 页 / 1316 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F103x8, STM32F103xB  
Electrical characteristics  
Table 9.  
Symbol  
General operating conditions (continued)  
Parameter Conditions  
Min  
Max  
Unit  
VDD  
0.3  
+
Standard IO  
–0.3  
2 V < VDD 3.6 V –0.3  
5.5  
5.2  
VIN  
I/O input voltage  
V
FT IO(3)  
BOOT0  
VDD = 2 V  
–0.3  
0
5.5  
LFBGA100  
454  
434  
339  
308  
444  
363  
624  
1000  
85  
LQFP100  
UFBGA100  
Power dissipation at TA = 85 °C  
for suffix 6 or TA = 105 °C for  
suffix 7(4)  
TFBGA64  
PD  
mW  
LQFP64  
LQFP48  
UFQFPN48  
VFQFPN36  
Maximum power dissipation  
Low power dissipation(5)  
Maximum power dissipation  
Low power dissipation(5)  
6 suffix version  
7 suffix version  
–40  
–40  
–40  
–40  
–40  
–40  
Ambient temperature for 6  
suffix version  
105  
105  
125  
105  
125  
TA  
TJ  
Ambient temperature for 7  
suffix version  
°C  
Junction temperature range  
1. When the ADC is used, refer to Table 46: ADC characteristics.  
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV  
between VDD and VDDA can be tolerated during power-up and operation.  
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.  
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal  
characteristics on page 93).  
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see  
Table 6.2: Thermal characteristics on page 93).  
5.3.2  
5.3.3  
Operating conditions at power-up / power-down  
Subject to general operating conditions for T .  
A
Table 10. Operating conditions at power-up / power-down  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VDD rise time rate  
VDD fall time rate  
0
tVDD  
µs/V  
20  
Embedded reset and power control block characteristics  
The parameters given in Table 11 are derived from tests performed under ambient  
temperature and V supply voltage conditions summarized in Table 9.  
DD  
Doc ID 13587 Rev 15  
39/105  
 
 
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