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STM32F103C8T7 参数 Datasheet PDF下载

STM32F103C8T7图片预览
型号: STM32F103C8T7
PDF下载: 下载PDF文件 查看货源
内容描述: 中密度高性能线的基于ARM的32位MCU,具有64或128 KB的闪存, USB , CAN ,7个定时器, 2的ADC , 9融为一体。接口 [Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces]
分类和应用: 闪存
文件页数/大小: 105 页 / 1316 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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STM32F103x8, STM32F103xB
Table 9.
Symbol
Electrical characteristics
General operating conditions (continued)
Parameter
Conditions
Standard IO
Min
–0.3
–0.3
–0.3
0
Max
V
DD
+
0.3
5.5
5.2
5.5
454
434
339
308
mW
444
363
624
1000
–40
–40
–40
–40
–40
–40
85
105
105
°C
125
105
125
V
Unit
V
IN
I/O input voltage
FT IO
(3)
BOOT0
2 V < V
DD
3.6 V
V
DD
= 2 V
LFBGA100
LQFP100
UFBGA100
P
D
Power dissipation at T
A
= 85 °C TFBGA64
for suffix 6 or T
A
= 105 °C for
LQFP64
suffix 7
(4)
LQFP48
UFQFPN48
VFQFPN36
Ambient temperature for 6
suffix version
T
A
Ambient temperature for 7
suffix version
T
J
Junction temperature range
7 suffix version
1. When the ADC is used, refer to
Maximum power dissipation
Low power dissipation
(5)
Maximum power dissipation
Low power dissipation
6 suffix version
2. It is recommended to power V
DD
and V
DDA
from the same source. A maximum difference of 300 mV
between V
DD
and V
DDA
can be tolerated during power-up and operation.
3. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see
5. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
J
max (see
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for T
A
.
Table 10.
Symbol
t
VDD
Operating conditions at power-up / power-down
Parameter
V
DD
rise time rate
V
DD
fall time rate
Conditions
Min
0
20
Max
Unit
µs/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in
are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Doc ID 13587 Rev 15
39/105