STM32F103xC, STM32F103xD, STM32F103xE
Output voltage levels
Electrical characteristics
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10. All I/Os are CMOS and TTL compliant.
Table 47. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
CMOS port(2)
IIO = +8 mA
VOL
0.4
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)
2.7 V < VDD < 3.6 V
VOH
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
TTL port(2)
IIO =+ 8mA
VOL
0.4
1.3
0.4
V
V
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)
2.7 V < VDD < 3.6 V
VOH
2.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
I
IO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)(4)
VOH
VDD–1.3
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
IIO = +6 mA
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)(4)
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data, not tested in production.
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