Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 46. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO input low
level voltage
–0.3
0.28*(VDD-2 V)+0.8 V
V
VIL
IO FT(1) input low level
voltage
–0.3
0.32*(VDD-2 V)+0.75 V
VDD+0.3
V
V
Standard IO input high
level voltage
0.41*(VDD-2 V)+1.3 V
VIH
IO FT(1) input high level
voltage
VDD > 2 V
5.5
5.2
0.42*(VDD-2 V)+1 V
200
V
VDD ≤ 2 V
Standard IO Schmitt
trigger voltage
hysteresis(2)
mV
mV
Vhys
IO FT Schmitt trigger
voltage hysteresis(2)
(3)
5% VDD
VSS ≤ VIN ≤ VDD
Standard I/Os
±1
3
Ilkg
Input leakage current (4)
µA
VIN= 5 V, I/O FT
Weak pull-up equivalent
resistor(5)
RPU
VIN = VSS
30
30
40
50
kΩ
Weak pull-down
RPD
CIO
VIN = VDD
40
5
50
kΩ
equivalent resistor(5)
I/O pin capacitance
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and
in Figure 44 and Figure 45 for 5 V tolerant I/Os.
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