STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
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Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol Parameter Min
tw(CLK)
Max
Unit
FSMC_CLK period
27.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
4
2
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
FSMC_CLK low to FSMC_NOE low
5
0
td(CLKL-AIV)
4
td(CLKL-NOEL)
td(CLKL-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
1.5
FSMC_CLK low to FSMC_NOE high
1.5
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
FSMC_D[15:0] valid data after FSMC_CLK high
7
7
2
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 8
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STMICROELECTRONICS [ ST ]
