Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 31. Synchronous non-multiplexed PSRAM write timings
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Table 38. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Max Unit
FSMC_CLK period
27.7
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
5
2
1
4
0
1
6
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
td(CLKL-AIV)
td(CLKL-NWEL)
td(CLKL-NWEH)
td(CLKL-Data)
FSMC_CLK low to FSMC_NWE high
FSMC_D[15:0] valid data after FSMC_CLK low
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
7
2
1
td(CLKL-NBLH)
1. CL = 15 pF.
FSMC_CLK low to FSMC_NBL high
2. Based on characterization, not tested in production.
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Doc ID 14611 Rev 8
STMICROELECTRONICS [ ST ]
