Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
(1)(2)
Table 35. Synchronous multiplexed NOR/PSRAM read timings
Symbol Parameter
tw(CLK)
Min
27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
2
5
2
4
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NOE low
0
td(CLKL-AIV)
td(CLKL-NOEL)
td(CLKL-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
1
FSMC_CLK low to FSMC_NOE high
0.5
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
12
0
6
FSMC_A/D[15:0] valid data before FSMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
ns
FSMC_A/D[15:0] valid data after FSMC_CLK high 0
ns
ns
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
8
2
1. CL = 15 pF.
2. Based on characterization, not tested in production.
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Doc ID 14611 Rev 8
STMICROELECTRONICS [ ST ]
