Electrical characteristics
Figure 30. SPI timing diagram - slave mode and CPHA = 0
STM32F103x4, STM32F103x6
NSS input
tc(SCK)
tSU(NSS)
SCK Input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
ta(SO)
MISO
OUT P UT
tsu(SI)
MOSI
I NPUT
M SB IN
th(SI)
ai14134c
th(NSS)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
LSB OUT
tv(SO)
MS B O UT
th(SO)
BI T6 OUT
tdis(SO)
B I T1 IN
LSB IN
Figure 31. SPI timing diagram - slave mode and CPHA = 1
(1)
NSS input
tSU(NSS)
SCK Input
tc(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
ta(SO)
MISO
OUT P UT
tsu(SI)
MOSI
I NPUT
M SB IN
tv(SO)
MS B O UT
th(SI)
th(SO)
BI T6 OUT
tdis(SO)
LSB OUT
B I T1 IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
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Doc ID 15060 Rev 5