Electrical characteristics
Figure 35. Typical connection diagram using the ADC
STM32F103x4, STM32F103x6
V
DD
STM32F103xx
Sample and hold ADC
V
0.6 V
T
converter
(1)
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 µA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
ai14150c
1. Refer to Table 46 for the values of RAIN, RADC and CADC
2.
.
C
parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown inFigure 36 or Figure 37,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 36. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
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6
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6
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6
33!
AIꢀꢊꢈꢈꢁ
1. The VREF+ input is available only on the TFBGA64 package.
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Doc ID 15060 Rev 5
STMICROELECTRONICS [ ST ]
