Pinouts and pin description
STM32F103x8, STM32F103xB
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
C6 B6
D6 A5
-
-
-
-
-
-
87
88
-
-
PD6
PD7
I/O FT
I/O FT
PD6
PD7
USART2_RX
USART2_CK
TIM2_CH2 /
PB3
TRACESWO
SPI1_SCK
A7 A8 39 A5 55 89 30
PB3
PB4
I/O FT
I/O FT
JTDO
TIM3_CH1/
PB4/
A6 A7 40 A4 56 90 31
JNTRST
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
C5 C5 41 C4 57 91 32
B5 B5 42 D3 58 92 33
PB5
PB6
I/O
PB5
PB6
I2C1_SMBAl
I2C1_SCL(8)
TIM4_CH1(8)
/
I/O FT
USART1_TX
USART1_RX
I2C1_SDA(8)
TIM4_CH2(8)
/
A5 B4 43 C3 59 93 34
D5 A4 44 B4 60 94 35
PB7
BOOT0
PB8
I/O FT
I
PB7
BOOT0
PB8
I2C1_SCL /
CANRX
B4 A3 45 B3 61 95
A4 B3 46 A3 62 96
-
-
I/O FT
TIM4_CH3(8)
I2C1_SDA/
CANTX
PB9
I/O FT
PB9
TIM4_CH4(8)
TIM4_ETR
D4 C3
C4 A2
-
-
-
-
-
-
97
98
-
-
PE0
PE1
I/O FT
I/O FT
S
PE0
PE1
E5 D3 47 D4 63 99 36
VSS_3
VDD_3
VSS_3
VDD_3
F5 C4 48 E4 64 100
1
S
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
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Doc ID 13587 Rev 14
STMICROELECTRONICS [ ST ]
