Electrical characteristics
Figure 23. ADC accuracy characteristics
E
G
1023
1022
1021
1LSB
IDEAL
V
–
V
DDA
SSA
= ----------------------------------------
-
STM32F103xx
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1024
(2)
E
T
7
6
5
4
3
2
1
0
1
V
SSA
2
3
4
1 LSB
IDEAL
E
O
E
L
E
D
(3)
(1)
E
T
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
5
6
7
1021 1022 1023 1024
V
DDA
ai14395
Figure 24. Typical connection diagram using the ADC
VDD
VT
0.6V
RAIN
AINx
VT
0.6V
RADC
12-bit A/D
conversion
CADC
STM32F103xx
VAIN
CAIN(1)
IL±1mA
ai14150
1. Refer to
for the values of R
ADC
and C
ADC
.
2. C
PARASITIC
must be added to C
AIN
. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high C
PARASITIC
value will downgrade conversion
accuracy. To remedy this, f
ADC
should be reduced.
56/67
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