Electrical characteristics
STM32F103xx
Wakeup time from low power mode
The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
■
■
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 7.
(1)
Table 21. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max Unit
(2)
Wakeup from Sleep mode
Wakeup on HSI RC clock
0.75 TBD
µs
tWUSLEEP
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 µs
4
7
TBD
TBD
(2)
µs
tWUSTOP
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
(3)
Wakeup from Standby mode
40
TBD
µs
tWUSTDBY
1. TBD stands for to be determined.
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
user application code reads the first instruction.
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.
5.3.8
PLL characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 7.
DD
(1)
Table 22. PLL characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max(2)
PLL input clock
PLL input clock duty cycle
8.0
MHz
%
fPLL_IN
40
16
60
72
fPLL_OUT PLL multiplier output clock
MHz
When PLL operates
(locked)
fVCO
tLOCK
tJITTER
VCO frequency range
PLL lock time
32
144
200
MHz
µs
Cycle to cycle jitter (+/-3Σ
peak to peak)
VDD is stable
TBD
TBD
%
1. TBD stands for to be determined.
2. Data based on device characterization, not tested in production.
38/67
STMICROELECTRONICS [ ST ]
