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STM32F103RBT6XXXTR 参数 Datasheet PDF下载

STM32F103RBT6XXXTR图片预览
型号: STM32F103RBT6XXXTR
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 微控制器和处理器外围集成电路PC通信时钟
文件页数/大小: 67 页 / 1083 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F103xx  
Electrical characteristics  
5.3.5  
Supply current characteristics  
The current consumption is measured as described in Figure 10: Current consumption  
measurement scheme.  
Maximum current consumption  
The MCU is placed under the following conditions:  
All I/O pins are in input mode with a static value at V or V (no load)  
DD SS  
All peripherals are disabled except if it is explicitly mentioned  
The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1  
HCLK  
wait state from 24 to 48 MHz and 2 wait states above)  
The parameters given in Table 11 are derived from tests performed under ambient  
temperature and V supply voltage conditions summarized in Table 7.  
DD  
(1)  
Table 11. Maximum current consumption in Run and Sleep modes  
Max(3)  
Symbol Parameter  
Conditions  
FHCLK Typ(2)  
Unit  
TA =  
TA=  
85 °C 105 °C  
72 MHz  
48 MHz  
36 MHz  
24 MHz  
36  
30  
22  
21  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
External clock with PLL, code running from  
Flash, all peripherals enabled (see RCC  
register description):  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
External clock, PLL stopped, code running  
from Flash, all peripherals enabled (see RCC  
register description):  
8 MHz  
10  
TBD  
TBD  
Supply  
current in  
Run mode  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
mA  
72 MHz  
48 MHz  
36 MHz  
24 MHz  
32  
22  
13  
11  
45  
31  
18  
15  
47  
33  
20  
17  
External clock with PLL, code running from  
RAM, all peripherals enabled (see RCC  
register description):  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
IDD  
External clock, PLL stopped, code running  
from RAM, all peripherals enabled (see RCC  
register description):  
8 MHz  
4.5  
TBD  
TBD  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
72 MHz  
48 MHz  
36 MHz  
24 MHz  
22  
14  
13  
10  
35  
23  
22  
17  
37  
25  
24  
19  
External clock with PLL, code running from  
RAM or Flash, all peripherals enabled (see  
RCC register description):  
Supply  
current in  
Sleep mode  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
mA  
External clock, PLL stopped, code running  
from RAM or Flash, all peripherals enabled  
(see RCC register description):  
8 MHz  
3.5  
TBD  
TBD  
fPCLK1= fHCLK/2, fPCLK2 = fHCLK  
1. TBD stands for to be determined.  
2. Typical values are measured at TA = 25 °C, and VDD = 3.3 V  
3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM.  
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