ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Table 17. Detailed Register Map
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R227
R228
R229
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R240
R241
R242
R244
R245
R246
R248
R249
R250
R252
R253
R254
CICR
FLAGR
RP0
Central Interrupt Control Register
Flag Register
87
33
34
36
36
38
38
40
40
40
40
00
Pointer 0 Register
xx
RP1
Pointer 1 Register
xx
PPR
Page Pointer Register
xx
Core
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P3DR
P4DR
P5DR
EITR
Mode Register
E0
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
xx
xx
N/A
xx
xx
FF
Port 1 Data Register
FF
I/O
Port
0:5
Port 2 Data Register
FF
150
Port 3 Data Register
1111 111x
Port 4 Data Register
FF
Port 5 Data Register
FF
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
00
105
106
106
106
162
107
161
161
161
161
162
EIPR
00
EIMR
00
INT
EIPLR
EIVR
FF
x6
0
NICR
00
WDTHR
WDTLR
WDTPR
WDTCR
WCR
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
FF
FF
WDT
FF
12
7F
P0C0
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 1 Configuration Register 0
Port 1 Configuration Register 1
Port 1 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
00
I/O
Port
0
P0C1
00
P0C2
00
P1C0
00
00
I/O
Port
1
P1C1
P1C2
00
2
150
P2C0
FF
I/O
Port
2
P2C1
00
P2C2
00
P3C0
1111 111x
0000 000x
0000 000x
I/O
Port
3
P3C1
P3C2
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STMICROELECTRONICS [ ST ]
