ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
FUNCTIONAL DESCRIPTION (Cont’d)
3.2.3 Operation
The memory has a register interface mapped in
memory space (segment 22h). All operations are
enabled through the FCR (Flash Control Register),
ECR (E3 TM Control Register).
If the RESET pin is activated during a write opera-
tion, the write operation is interrupted. In this case
the user must repeat this last write operation fol-
lowing power on or reset. If the internal supply volt-
age drops below the V threshold, a reset se-
IT-
All operations on the Flash must be executed from
quence is generated automatically by hardware.
another memory (internal RAM, E3 TM, external
memory).
3 TM
Flash (including TestFlash) and E
are inde-
3.2.4 E3 TM Update Operation
pendent, this means that one can be read while
the other is written. However simultaneous Flash
and E3 TM write operations are forbidden.
3 TM
The update of the E
content can be made by
pages of 16 consecutive bytes. The Page Update
operation allows up to 16 bytes to be loaded into
the RAM buffer that replace the ones already con-
tained in the specified address.
An interrupt can be generated at the end of a
3 TM
Flash or an E
write operation: this interrupt is
multiplexed with an external interrupt EXTINTx
(device dependent) to generate an interrupt INTx.
Each time a Page Update operation is executed in
the E3 TM, the RAM buffer content is programmed
in the next free block relative to the specified page
(the RAM buffer is previously automatically filled
with old data for all the page addresses not select-
ed for updating). If all the 4 blocks of the specified
page in the current E3 TM sector are full, the page
content is copied to the complementary sector,
that becomes the new current one.
The status of a write operation inside the Flash
and the E3 TM memories can be monitored through
the FESR[1:0] registers.
Control and Status registers are mapped in mem-
ory (segment 22h), as shown in the following fig-
ure.
Figure 32. Control and Status Register Map.
Register Interface
After that the specified page has been copied to
the next free block, one erase phase is executed
on the complementary sector, if the 4 erase phas-
es have not yet been executed. When the selected
page is copied to the complementary sector, the
remaining 63 pages are also copied to the first
block of the new sector; then the first erase phase
is executed on the previous full sector. All this is
executed in a hidden manner, and the End Page
Update Interrupt is generated only after the end of
the complete operation.
/
FCR
ECR
FESR0
FESR1
221000h
221001h
221002h
221003h
224000h
224001h /
/
224002h
224003h
/
In order to use the same data pointer register
3
TM
At Reset the two status pages are read in order to
detect which is the sector that is currently mapping
(DPR) to point both to the E
(220000h-
2203FFh) and to these control and status regis-
3
the E TM, and in which block each page is
3 TM
ters, the Flash and E
control registers are
mapped. A system defined routine written in Test-
Flash is executed at reset, so that any previously
aborted write operation is restarted and complet-
ed.
mapped not only at page 0x89 (224000h-
224003h) but also on page 0x88 (221000h-
221003h).
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STMICROELECTRONICS [ ST ]
