4 Architecture
ST40RA
4
4.1
Architecture
Overview
The ST40RA combines an SH-4, 32-bit microprocessor with a wide range of interfaces to external
peripherals. This section briefly describes each of the features of the ST40RA.
4.2
4.2.1
ST40 system
SuperH ST40 SH-4 core
Figure 1
illustrates the system architecture of the ST40 SH-4 core. The following section briefly
describes the features and performance of the core.
CPU
UBC
FPU
32-bit add (instruction)
32-bit data (instruction)
32-bit address (data)
64-bit data (store)
32-bit data (load)
32-it data (store)
Lower 32-bit data
Lower 32-bit data
ICache 8 Kbytes
ITLB
Cache and TLB
controller
UTLB
DCache 16 Kbytes
29bit add
Figure 1: ST40 SH-4 core architecture
Central processing unit
The central processing unit is built around a 32-bit RISC, two-way superscalar architecture.
Operating at 166 MHz it runs with high code density using fixed length 16-bit instructions. It has a
load/store architecture, delayed branch instruction capability and an on-chip multiplier. It uses a
five-stage pipeline.
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STMicroelectronics
ADCS 7260755H
32bit data
32bit data
Upper 32-bit data
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