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ST40RA150XHA 参数 Datasheet PDF下载

ST40RA150XHA图片预览
型号: ST40RA150XHA
PDF下载: 下载PDF文件 查看货源
内容描述: 32位嵌入式设备的SuperH [32-bit Embedded SuperH Device]
分类和应用:
文件页数/大小: 94 页 / 778 K
品牌: STMICROELECTRONICS [ ST ]
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ST40RA  
32-bit Embedded SuperH Device  
DATASHEET  
Integer & FP  
execution units  
JTAG  
Debug  
JTAG  
UDI  
Registers  
Mailbox  
24 data  
SCIF  
MMU  
D Cache  
MMU  
I Cache  
PIO  
interface  
SCIF  
2 channel  
control  
5 channel  
DMA  
controller  
Timer (TMU)  
Real-time clock  
Interrupt ctrl  
Clock ctrl  
PLLs  
Cbus Bridge/  
MPX  
SuperHyway I/F  
Coprocessor  
EMI  
SuperHyway  
32 data  
Flash  
PCI I/F 66MHz  
ST40 Local Memory I/F  
32 data  
PCI Peripherals  
64 data  
SDRAM  
Peripherals  
Memory protection and VM system support  
Overview  
64-entry unified TLB, 4-entry instruction TLB  
4 Gbytes address space  
The ST40RA is the first member of the ST40 family. Based  
on the SH-4, SuperH CPU core from SuperH Inc, the  
ST40RA is designed to work as a standalone device, or as  
part of a two chip solution for application specific systems.  
Standard ST40 peripherals  
2 synchronous serial ports with FIFO (SCIF)  
Timers and a real-time clock  
Example applications the ST40RA is designed for include  
digital consumer, embedded communications, industrial  
and automotive. The high connectivity of the ST40 through  
its PCI bus and its dual memory uses makes it a versatile  
device, ideal for data-intensive and high performance  
applications.  
IO devices  
Mailbox register for interprocessor communication  
Additional PIO  
Bus interfaces  
System features  
Local memory interface SDRAM & DDR SDRAM  
Up to 100 MHz (1.6 Gbytes/s peak throughput)  
PCI interface - 32-bit, 66/33 MHz, 3.3 V  
Enhanced memory interface (EMI)  
32-bit SuperH CPU  
64-bit hardware FPU (1.16 GFLOPS)  
128-bit vector unit for matrix manipulations  
166 MHz, 300 MIPS (DMIPS 1.1)  
Up to 664 Mbytes/s CPU bandwidth  
32-bit bus, up to 83 MHz, for attaching peripherals  
High-speed, sync mode, burst flash ROM support  
SDRAM support  
Direct mapped, on-chip, ICache (8 Kbytes) and DCache  
(16 Kbytes)  
High-performance 5-channel DMA engine,  
MPX initiator and target interface  
Programmable MPX bus arbiter  
supporting 1D or 2D block moves and linked lists  
SuperHyway internal interconnect  
High throughput, low latency, split transaction packet  
router  
13 August 2003  
ADCS7260755H  
STMicroelectronics  
1/94  
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