Electrical characteristics
ST10F276E
23.8.19 Demultiplexed bus
VDD = 5V 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,
ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40 MHz CPU clock without wait states).
Table 105. Demultiplexed bus
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
4 + tA
TCL - 8.5 + tA
TCL - 11 + tA
t5 CC ALE high time
-
-
-
-
ns
ns
1.5 + tA
t6 CC Address setup to ALE
Address/Unlatched CS
t80 CC setup to RD, WR
(with RW-delay)
12.5 + 2tA
0.5 + 2tA
2TCL - 12.5 + 2tA
TCL - 12 + 2tA
-
-
-
-
ns
ns
Address/Unlatched CS
t81 CC setup to RD, WR
(no RW-delay)
RD, WR low time
t12 CC
15.5 + tC
28 + tC
-
2TCL - 9.5 + tC
-
-
-
ns
ns
ns
(with RW-delay)
RD, WR low time
t13 CC
3TCL - 9.5 + tC
-
-
(no RW-delay)
RD to valid data in
t14 SR
6 + tC
2TCL - 19 + tC
(with RW-delay)
RD to valid data in
t15 SR
18.5 + tC
3TCL - 19 + tC
3TCL - 20 + tA + tC
4TCL - 30 + 2tA + tC
-
-
-
-
-
-
ns
ns
ns
(no RW-delay)
17.5 + tA + tC
20 + 2tA + tC
t16 SR ALE low to valid data in
Address/Unlatched CS to
valid data in
t17 SR
Data hold after RD
t18 SR
0
-
-
0
-
-
ns
ns
ns
rising edge
Data float after RD rising
t20 SR edge
16.5 + tF
4 + tF
2TCL - 8.5 + tF + 2tA
TCL - 8.5 + tF + 2tA
(with RW-delay)(1)
Data float after RD rising
t21 SR
-
-
edge (no RW-delay)(1)
10 + tC
4 + tF
2TCL - 15 + tC
TCL - 8.5 + tF
t22 CC Data valid to WR
t24 CC Data hold after WR
-
-
-
-
ns
ns
ALE rising edge after RD,
WR
-10 + tF
0 + tF
-10 + tF
0 + tF
t26 CC
-
-
-
-
-
-
ns
ns
ns
Address/Unlatched CS
t28 CC
hold after RD, WR (2)
Address/Unlatched CS
hold after WRH
- 5 + tF
- 5 + tF
t28hCC
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
