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ST10F276S-4T3 参数 Datasheet PDF下载

ST10F276S-4T3图片预览
型号: ST10F276S-4T3
PDF下载: 下载PDF文件 查看货源
内容描述: 16位MCU与MAC单元832 KB的闪存和68 KB的RAM [16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM]
分类和应用: 闪存
文件页数/大小: 235 页 / 2491 K
品牌: STMICROELECTRONICS [ ST ]
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Register set  
ST10F276E  
hwbit  
Bit that is set/cleared by hardware is written in bold  
22.3  
General purpose registers (GPRs)  
The GPRs form the register bank that the CPU works with. This register bank may be  
located anywhere within the internal RAM via the Context Pointer (CP). Due to the  
addressing mechanism, GPR banks reside only within the internal RAM. All GPRs are bit-  
addressable.  
Table 65. General purpose registers (GPRs)  
Physical  
address  
8-bit  
address  
Reset  
value  
Name  
Description  
R0  
(CP) + 0  
F0h  
CPU general purpose (word) register R0  
CPU general purpose (word) register R1  
CPU general purpose (word) register R2  
CPU general purpose (word) register R3  
CPU general purpose (word) register R4  
CPU general purpose (word) register R5  
CPU general purpose (word) register R6  
CPU general purpose (word) register R7  
CPU general purpose (word) register R8  
CPU general purpose (word) register R9  
CPU general purpose (word) register R10  
CPU general purpose (word) register R11  
CPU general purpose (word) register R12  
CPU general purpose (word) register R13  
CPU general purpose (word) register R14  
CPU general purpose (word) register R15  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
UUUUh  
R1  
(CP) + 2  
F1h  
F2h  
F3h  
F4h  
F5h  
F6h  
F7h  
F8h  
F9h  
FAh  
FBh  
FCh  
FDh  
FEh  
FFh  
R2  
(CP) + 4  
R3  
(CP) + 6  
R4  
(CP) + 8  
R5  
(CP) + 10  
(CP) + 12  
(CP) + 14  
(CP) + 16  
(CP) + 18  
(CP) + 20  
(CP) + 22  
(CP) + 24  
(CP) + 26  
(CP) + 28  
(CP) + 30  
R6  
R7  
R8  
R9  
R10  
R11  
R12  
R13  
R14  
R15  
The first eight GPRs (R7...R0) may also be accessed bytewise. Other than with SFRs,  
writing to a GPR byte does not affect the other byte of the respective GPR. The respective  
halves of the byte-accessible registers have special names:  
Table 66. General purpose registers (GPRs) bytewise addressing  
Physical  
address  
8-bit  
address  
Reset  
value  
Name  
Description  
RL0  
(CP) + 0  
(CP) + 1  
(CP) + 2  
(CP) + 3  
F0h  
CPU general purpose (byte) register RL0  
CPU general purpose (byte) register RH0  
CPU general purpose (byte) register RL1  
CPU general purpose (byte) register RH1  
UUh  
UUh  
UUh  
UUh  
RH0  
RL1  
RH1  
F1h  
F2h  
F3h  
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Doc ID 12303 Rev 3  
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