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MIC2593-2BTQ 参数 Datasheet PDF下载

MIC2593-2BTQ图片预览
型号: MIC2593-2BTQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双插槽PCI热插拔控制器 [Dual-Slot PCI Hot Plug Controller]
分类和应用: 控制器PC
文件页数/大小: 26 页 / 175 K
品牌: STMICROELECTRONICS [ ST ]
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MIC2593  
Micrel  
duremaybeused. ToperformaReceive_Byteoperation, the  
host sends an address byte to select the slave MIC2593, with  
the R/W bit set to the high (read) state, and then retrieves the  
data byte. Figures 9 through 11 show the formats for these  
data read and data write procedures.  
Inputs  
MIC2593 Slave Address  
A2  
0
A1  
0
A0  
0
Binary  
1000 000  
1000 001  
1000 010  
1000 011  
1000 100  
1000 101  
1000 110  
1000 111  
Hex  
80  
b
b
b
b
b
b
b
b
h
0
0
1
82  
h
The Command Register is eight bits (one byte) wide. This  
byte carries the address of the MIC2593s register to be  
operated upon. The command byte values corresponding to  
the various MIC2593 register addresses are shown in Table  
4. Command byte values other than 0000 0XXX = 00 - 07  
h
0
1
0
84  
h
0
1
1
86  
h
1
0
0
88  
h
b
h
1
0
1
8A  
are reserved and should not be used.  
h
1
1
0
8C  
h
1
1
1
8E  
h
Table 3. MIC2593 SMBus Addressing  
MIC2593 Register Set and Programmers Model  
Target Register  
Command Byte Value Power-On  
Default  
Label  
Description  
Read  
Write  
n/a  
RESERVED  
RESERVED  
CNTRLA  
CNTRLB  
STATA  
Do not Use  
00  
01  
02  
03  
04  
05  
06  
n/a  
n/a  
h
h
h
h
h
h
h
Do not Use  
n/a  
Control Register Slot A  
Control Register Slot B  
Slot A Status  
02  
00  
h
h
03  
00  
h
h
04  
00  
h
h
STATB  
Slot B Status  
05  
00  
h
h
CS  
Common Status Register  
Reserved / Do Not Use  
06  
xxxx 0000  
h
b
Reserved  
07 - FF  
07 - FF  
Undefined  
h
h
h
h
Table 4. MIC2593 Register Addresses  
MIC2593 Slave Address  
Command Byte to MIC2593  
Data Byte to MIC2593  
S
1
0
0
1
A2 A1 A0  
0
A
0
0
0
0
0
0
X
X
A
D7 D6 D5 D4 D3 D2 D1 D0 A P  
DATA  
CLK  
R/W = WRITE  
ACKNOWLEDGE  
ACKNOWLEDGE  
ACKNOWLEDGE  
START  
STOP  
Master to slave transfer,  
i.e., DATA driven by master.  
Slave to master transfer,  
i.e., DATA driven by slave.  
Figure 9. WRITE_BYTE Protocol  
MIC2593 Slave Address  
Command Byte to MIC2593  
MIC2593 Slave Address  
Data Read From MIC2593  
S
1
0
0
1 A2 A1 A0 0  
A
0
0
0
0
0
0
X
X
A
S
1
0
0
1 A2 A1 A0 1  
A
D7 D6 D5 D4 D3 D2 D1 D0 /A P  
DATA  
CLK  
R/W = WRITE  
ACKNOWLEDGE  
ACKNOWLEDGE  
R/W = READ  
ACKNOWLEDGE NOT ACKNOWLEDGE  
START  
START  
STOP  
Master to slave transfer,  
i.e., DATA driven by master.  
Slave to master transfer,  
i.e., DATA driven by slave.  
Figure 10. READ_BYTE Protocol  
Byte Read from MIC2593  
MIC2593 Slave Address  
S
1
0
0
1
A2 A1 A0  
1
A
D7 D6 D5 D4 D3 D2 D1 D0 /A P  
DATA  
CLK  
R/W = READ  
ACKNOWLEDGE NOT ACKNOWLEDGE  
START  
STOP  
Master to slave transfer,  
i.e., DATA driven by master.  
Slave to master transfer,  
i.e., DATA driven by slave.  
Figure 11. RECEIVE_BYTE Protocol  
April 2004  
15  
M9999-042204