MIC2593
Micrel
HPI-only Control Applications
enabled after t
. The timing response diagram of Figure 8
POR
illustrates a Hot Plug Interface operation where an overcur-
rent fault is detected by the MIC2593 controller after initiating
a power-up sequence. The figure illustrates the output re-
sponse of /FAULT, /INT, VAUX[A/B] supplies, and an exter-
nal MOSFET control MAIN[A/B] output supply, either 3.3V or
5V.
In applications where the MIC2593 is controlled only by the
HPI, SMBus signals SCL, SDA, and /INT signals are con-
nected to VSTBY as shown in Figure 6. In this configuration,
theMIC2593’s/FAULT[A/B]outputsareactivatedafterpower-
on-reset and become asserted when:
Either or both external ON[A/B] and AUXEN[A/B] input sig-
nals are asserted, AND
MIC2593 SMBus Address Configuration
The MIC2593 responds to its own unique address which is
assigned using A2, A1, and A0. These represent the 3 LSBs
of its 7-bit address, as shown in Table 3. These address bits
are assigned only during power up of the VSTBY[A/B] supply
input. These three bits allow up to eight MIC2593 devices in
a single system. These pins are either grounded or left
unconnected to specify a logical 0 or 1, respectively. A pin
• 12VIN[A/B], 12MVIN[A/B], 5VIN[A/B], 3VIN[A/B],
or VSTBY[A/B] input voltage is lower than its
respective ULVO threshold, OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its filter timeout[A/B] has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature exceeds 140°C, OR
designated as a logical 1 may also be pulled up to V
.
STBY
Serial Port Operation
• The MIC2593’s global die temperature exceeds
160°C
The MIC2593 uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the device’s
slave address, with the R/W bit (LSB) set to the low (write)
state, followed by a command byte and a data byte. The
SMBus Read_Byte operation is similar, but is a composite
write and read operation: the host first sends the device’s
slave address followed by the command byte, as in a write
operation.Anew“Start”bitmustthenbesenttotheMIC2593,
followed by a repeat of the slave address with the R/W bit set
to the high (read) state. The data to be read from the part may
then be clocked out. There is one exception to this rule: If the
location latched in the pointer register from the last write
operation is known to be correct (i.e., points to the desired
registerwithintheMIC2593), thenthe“Receive_Byte”proce-
Inordertoclear/FAULT[A/B]outputsonceasserted,ON[A/B]
and/orAUXEN[A/B]inputsignalsmustbede-asserted.Please
see the /FAULT[A/B] pin description for additional informa-
tion.
Hot Plug Interface (HPI) Operation
Once the input supplies are above their respective UVLO
thresholds, the Hot Plug Interface can be utilized for power
control by enabling the control input pins (AUXEN[A/B] and
ON[A/B]) for each slot. In order for the MIC2593 to switch on
theVAUXsupplyforeitherslot, theAUXEN[A/B]controlmust
be enabled after the power-on-reset delay, t
(typically
POR
500µs), has elapsed. The MAIN output supplies can also be
+3.3V
UVLO
VSTBY
VIH
VIH
AUXEN[A/B]
VIL
0
t
POR
AUX_OUT[A/B]
0
ILIM(AUX)
t
FLT
IAUX_OUT[A/B]
ISTEADY-STATE
0
VIH
VIH
ON[A/B]
VIL
0
MAIN_OUT[A/B]
0
ILIM(MAIN)
t
FLT
I
I
M
A
I
N
_
O
U
T
[
A
/
B
]
S
T
E
A
D
Y
-
S
T
A
T
E
0
/FAULT_[A/B]
0
*
*
/INT*
0
* /INT de-asserted by software
Figure 8. Hot Plug Interface Operation
M9999-042204
14
April 2004
STMICROELECTRONICS [ ST ]
