M95320, M95640, M95320-x, M95640-x
Connecting to the SPI bus
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
V
SS
V
CC
R
(2)
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
V
CC
V
SS
R
(2)
SPI Memory
Device
R
(2)
C Q D
V
CC
V
SS
SPI Memory
R
(2)
Device
SPI Memory
Device
C Q D
V
CC
V
SS
SPI Bus Master
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the t
SHCH
requirement is met).
9/44
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