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M95640-WMN6TP/P 参数 Datasheet PDF下载

M95640-WMN6TP/P图片预览
型号: M95640-WMN6TP/P
PDF下载: 下载PDF文件 查看货源
内容描述: [8KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 47 页 / 620 K
品牌: STMICROELECTRONICS [ ST ]
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M95640-W M95640-R M95640-DF  
Instructions  
When the highest address is reached, the address counter rolls over to zero, allowing the  
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a  
single READ instruction.  
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip  
Select (S) signal can occur at any time during the cycle.  
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.  
6.6  
Write to Memory Array (WRITE)  
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven  
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted  
in, on Serial Data Input (D).  
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input  
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a  
period t (as specified in AC characteristics in Section 9: DC and AC parameters), at the  
W
end of which the Write in Progress (WIP) bit is reset to 0.  
Figure 12. Byte Write (WRITE) sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
20 21 22 23 24 25 26 27 28 29 30 31  
C
Instruction  
16-Bit Address  
Data Byte  
15 14 13  
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance  
AI01795D  
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.  
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte  
has been latched in, indicating that the instruction is being used to write a single byte.  
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte  
of input data is shifted in, so that more than a single byte, starting from the given address  
towards the end of the same page, can be written in a single internal Write cycle.  
Each time a new data byte is shifted in, the least significant bits of the internal address  
counter are incremented. If more bytes are sent than will fit up to the end of the page, a  
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size  
are overwritten from location 0 of the same page.  
Doc ID 16877 Rev 16  
23/47  
 
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