M93C86, M93C76, M93C66, M93C56, M93C46
Table 6.
Instruction
Instructions
Instruction set for the M93C56 and M93C66
x8 origination (ORG = 0)
Description
Start Op-
bit code
Address
(1) (2)
x16 origination (ORG = 1)
Data
Q15-Q0
D15-D0
27
11
11
11
11
D15-D0
27
Required
clock cycles
Data
Q7-Q0
D7-D0
Required Address
(1) (3)
clock cycles
A7-A0
20
12
12
12
12
A7-A0
11XX
XXXX
00XX
XXXX
A7-A0
10XX
XXXX
01XX
XXXX
READ
WRITE
WEN
WDS
ERASE
ERAL
WRAL
Read Data from
Memory
Write Data to
Memory
Write Enable
Write Disable
Erase Byte or
Word
Erase All
Memory
Write All Memory
with same Data
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A8-A0
A8-A0
1 1XXX
XXXX
0 0XXX
XXXX
A8-A0
1 0XXX
XXXX
0 1XXX
XXXX
D7-D0
20
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 7.
Instruction set for the M93C76 and M93C86
x8 Origination (ORG = 0)
x16 Origination (ORG = 1)
Required
clock
cycles
Start Op-
bit code Address
(1),
(2)
Instruction
Description
Data
Required
Address
clock
(1) (3)
cycles
A9-A0
22
14
14
14
14
A9-A0
11 XXXX
XXXX
00 XXXX
XXXX
A9-A0
10 XXXX
XXXX
Data
READ
WRITE
WEN
WDS
ERASE
ERAL
WRAL
Read Data from
Memory
Write Data to
Memory
Write Enable
Write Disable
Erase Byte or Word
Erase All Memory
Write All Memory
with same Data
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A10-A0
A10-A0
11X XXXX
XXXX
00X XXXX
XXXX
A10-A0
10X XXXX
XXXX
01X XXXX
XXXX
Q7-Q0
D7-D0
Q15-Q0
D15-D0
29
13
13
13
13
29
D7-D0
22
01 XXXX
D15-D0
XXXX
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
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