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M27C2001-12F1TR 参数 Datasheet PDF下载

M27C2001-12F1TR图片预览
型号: M27C2001-12F1TR
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位( 256Kb的×8) UV EPROM和OTP EPROM [2 Mbit (256Kb x 8) UV EPROM and OTP EPROM]
分类和应用: 存储内存集成电路可编程只读存储器电动程控只读存储器
文件页数/大小: 25 页 / 228 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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Device operation
M27C2001
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C2001 is in the programming mode when V
PP
input is at 12.75V, E is at V
IL
and P is
pulsed to V
IL
. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be
6.25 ± 0.25V.
2.6
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II
consists of applying a sequence of 100µs program pulses to each byte until a correct verify
occurs (see
During programming and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Figure 5.
Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
P = 100µs Pulse
NO
++n
= 25
YES
NO
VERIFY
YES
Last
Addr
NO
++ Addr
FAIL
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI00715C
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