M25PE10, M25PE20
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Standby mode and not transferring da-
ta:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
TSL RP
TSL RP
TSL
RP
AI10741B
Note: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
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STMICROELECTRONICS [ ST ]
